The present invention relates to semiconductor devices, and more particularly, to methods of forming and the resultant structures formed having cylindrical or substantially cylindrical wires for reducing both induced mechanical stresses on the structure and the line-to-line capacitance.
Integrated circuits (ICs) are fabricated by building multiple layers of wiring and passivation on substrates (wafers) that contain semiconductor devices. Often, interconnect metal conductive layers are connected to each other, and to the substrate, by patterned insulative layers residing over and under such interconnect metal conductive layers. These insulative layers are commonly composed of a dielectric material. The openings, such as trenches and vias, are etched into the insulative layers, by damascene or dual damascene processing, in locations where conductive wires or contacts are desired between conductive regions. These conductive regions may include previously deposited patterned metal layers, or conductive substrate layers underlying the insulative layer and metal patterns deposited on the insulative layer. The openings are then filled with metallization to form the conductors for electrically connecting devices located on different metallization levels of the IC.
In the fabrication of ICs, the insulative layers are often composed of dielectric materials having low dielectric constants. However, as the dielectric constant (low-k) of the material is lowered, the insulator material becomes mechanically weaker, and as such, it becomes significantly easier to crack or damage these low-k dielectric materials. The susceptibility of cracking and damage to low-k-dielectric materials increases, for example, as a result of the temperature cycling and/or temperature/humidity stressing of the IC. The presence of device interconnects, such as filled vias and/or rectangular trenches within the low-k dielectric layers, further increase stresses on the dielectric layer, which in turn, increase its susceptibility to cracking and damage. For instance, during sintering, stresses are primarily built up in the dielectric layer during the cool down cycle, whereby the dielectric layer is put into tension near any metal feature, making it prone to failure by cracking. This problem is most acute near the vias.
Referring to FIGS. 1A–1B, rectangular trench openings 12 are commonly formed by patterning and etching insulative layers, such as dielectric layer 10. These rectangular trench openings 12 extend horizontally into the dielectric layer 10, such that once filled with metallization, horizontal conductors, i.e. wires, have been formed by the horizontally applied patterns. However, as is shown, both the upper corners 14 and lower comers 16 of the rectangular trench opening 12 are formed at substantially 90° angles. It is these 90° angled corners 14 and 16 that increase the stresses on the dielectric layer, and thus increase susceptibility of the low-k dielectric layer to cracking or damage.
FIG. 1B shows the sharp 90° angled comers 14 may be eliminated by concaving downward the upper comers 14 to result in substantially flattened upper recessed comers 18 of trench 13. This is generally accomplished by a physical sputtering process, whereby the 90° angled corners 14 are roughened during the sputter processing, such that portions of the upper comers 14 are removed and the recessed comers 18 formed. This sputtering yield cross section is a function of the desired angle at the recessed comers 18, with a maximum angle of 45° at the upper recessed comers 18, as shown in FIG. 1B.
However, in recessing the upper 90° angled corners 14, the lower corners 16 remain at substantially 90° angles within trench 13. Thus, these 90° angled lower comers 16 continue to be propagation and nucleation points for potential cracks within the dielectric layer 10. Further, once trench 13 is filled with metallization, the wire formed remains to have a substantially rectangular cross-section shape. As circuit densities continually decrease for advanced logic and memory chips, the device and wire dimensions are scaled down, while the chip size is being increased. These more densely populated circuits are requiring that the rectangular wires be placed closer together, thus increasing the wiring capacitance between adjacent wires. That is, the capacitively coupled noise between neighboring rectangular shaped lines will become very severe. In addition, when the upper trench comers are rounded concave downward, the occurrence of undesired wire shorts between adjacent trenches increases, due to residual metal, which degrades the IC yield and/or reliability.
The trench opening may be formed with a microtrenched profile 31 (FIG. 2A), a slightly rounded bottom profile 33 (FIG. 2B), or alternatively, the microtrenched profile 31 and the slightly rounded bottom profile 33 may be processed together such that a flat bottom trench profile 35 is formed (FIG. 2C) in a rectangular trench opening 22, which has upper 24 and lower 26 comers at substantially 90° angles. However, once the trench openings of FIGS. 2A–2C are filled with metallization, the conductors form all substantially in the shape of rectangular parallelepipeds. Each of these rectangular parallelepipeds have at least one sharp corner and/or a flat edge, and as such, suffer from the above problems of propagation and nucleation points for potential cracks within the dielectric layer 10, as well as increased capacitively coupled noise between neighboring rectangular parallelepiped conductors.
Therefore, a need continues to exist in the art for improved methods and interconnect structures that significantly eliminate the problems of propagation and nucleation points for potential cracks within a low-k dielectric layer associated with substantially rectangular conductors, as well as reduce capacitively coupled noise between neighboring conductors.